Logic products on integrated circuit chips need to be tested to determine if there were errors during manufacturing that could result in faulty operation. To test these manufactured chips, devices called testers are used. Test patterns are generated to test faults (which are modeled to imitate physical defects). A defect is an unintended difference between implemented hardware and its intended design. These test patterns are applied to manufactured chips to determine if they are defective.
In order to make the testing of a logic product (or chip) easier, scan latches are added to it. These scan latches are chained together to form scan chains. The scan latches are filled with certain values through probes on the tester. The scan latches are used to launch values into the combinational logic under test and to measure values from the combinational logic. The values in the scan latches can be flushed out to compare with the “good” or expected values.
If the logic product has a defect, the test that shows up the fault that models this defect would result in a different response to the expected value.
During fabrication, wafers containing many chips are typically manufactured. These are then subject to a preliminary test to eliminate faulty chips. Good chips are then cut out of the wafer and are then packaged; e.g., into a module. This is typically followed by a more extensive module test before shipping good parts out of module test to the customer.
Automatic Test Pattern Generation (ATPG) is an electronic design method used to find input or test sequences (test vectors) that, when applied to a digital circuit, enable testers to distinguish between the correct circuit behavior and the faulty circuit behavior caused by defects. The acronym ATPG is also used to describe an Automatic Test Pattern Generator. The generated vectors are applied to the inputs of circuits under test. Upon receipt of each test vector (e.g., patterns of ones and zeros), the circuit under test responds by producing responses at its outputs (e.g., patterns of ones and zeros). If the circuit under test is operating properly, the response at each output of the circuit will match expected responses for each test vector. If a fault exists, a mismatch occurs. A fault is a representation of a defect at an abstracted function level.
There are two major ATPG methods: pseudorandom and deterministic ATPG. When faults on the design are specifically targeted by the test pattern generator to create tests, this is called deterministic ATPG. Test patterns generated are then loaded onto the design through a tester. Algorithmic methods for test generation are examples of deterministic ATPG, since the tests are systematically developed with a definite outcome for the targeted faults. One form of deterministic ATPG is described in U.S. Pat. No. 6,385,750 to Kapur et al., which is incorporated herein by reference.
Some chips designs, such as some Application-Specific Integrated Circuit (ASIC) chip designs, require a large number of deterministic test patterns from an Automatic Test Pattern Generator to reach the final maximum test coverage. This large number of test patterns may not fit in the buffer of the Automatic Test Pattern Generator and therefore may reduce the amount of testing of the circuit under test that takes place. Large amounts of test patterns also require longer test application times and ATPG time.
Some chips include built-in self test (BIST) logic. BIST on-chip logic generates test patterns on the fly using ‘pseudo-random’ patterns that detect faults (by luck) based test methods are popular in the industry. However, the quality of such BIST tests (and the test coverage that can be achieved) is not very high. Also, diagnostics of faulty chips is quite difficult. Due to these reasons, most ASICs use test patterns generated deterministically by a test pattern generator tool (that specifically target faults on the chip design) that provides higher test coverage. These test patterns are later loaded onto manufactured chips through testers.
Test pattern insertion is frequently used as a method to improve test coverage when BISTs are involved. A look into some of the solutions to similar problems involving test point insertion shows that many of them discuss improving pseudo-random testability. These are for BIST-based test solutions. The emphasis there is on improved test coverage (pattern count is not an issue as tests are generated on-chip). Test points introduced into the design through these methods do not work as well when test patterns are generated through deterministic methods where test coverage is already good but test volumes need to be kept low.
Some other solutions use test point insertion algorithms (algorithms that can be applied to a design that make suggestions about where test points can be added to improve testability) that have a ‘cost function’ associated with each node in the design. See “Test Point Insertion for Compact Self Tests,” by M. J. Geuzebroek, J. Th. Van der Linden, and A. J. van de Goor. Nodes that are less testable (determined by probabilities of controlling and observing ‘0’s and ‘1’s at that node) are assigned a higher cost. Test points (observe and control) are added at the ‘costliest’ nodes to decrease the cost function. A typical drawback with using this approach is that these algorithms are independent of the test pattern generator tool. If the cost function is not compatible with the algorithm that the test generator uses for creating test patterns, test point insertion will not be that effective.
Other solutions involve analyzing controllability and observability indices to determine where test points can be inserted. See “Essentials of Electronic Testing,” by Michael L. Bushnell, and Vishwani D. Agrawal. However, re-converging signals may correlate and controllability calculations may become inaccurate at the re-convergence point. Controllability and observability index calculations assume that each node in the design can be independently controlled. A re-convergence point occurs when, for example, a net splits into two, and the two child nets converge at the inputs of a downstream logic gate (like an ‘AND’ or an ‘OR’ for example). Since they originate from the same parent net, these two nodes at the input of the downstream gate cannot be independently controlled and the indices calculated at this point are inaccurate.
Random Resistant Fault Analysis (see, e.g., U.S. Pat. No. 6,532,571 to Gabrielson et al.; and U.S. Pat. No. 6,671,838 to Koprowski et al., both of which are incorporated herein by reference) is a tool that can find places to add test points to aid in detecting faults randomly, but does not necessarily put test points where deterministic ATPG needs them. A point that may appear random resistant can be simple for deterministic ATPG to test. Further, it is difficult to determine the starting point from which to run a random resistant fault analysis. The starting point should be at some point relatively high in the test coverage curve to obtain a useful result.
U.S. Pat. No. 6,385,750 to Kapur et al. discloses monitoring fault propagation to determine nets in the design to which faults are propagated as the faults are being simulated. Nets at which fault propagation discontinues (e.g., de-sensitized) are also monitored. Based on the fault propagation information, test points are selectively inserted to maximize the fault coverage of the set of test patterns. The method of U.S. Pat. No. 6,385,750 is directed more towards increasing fault coverage. Further, the method of U.S. Pat. No. 6,385,750 is a tool developer's solution and has to be stitched into the test generation tool.
Advances in technology, as we enter the sub-micron era, have resulted in increased logic density. With increased density and complexity of logic products, it is becoming increasingly difficult to test hardware designs. Test pattern volumes have gone up, increasing the time spent at the tester, hence increasing test costs.